NAND flash continues to evolve with higher data density to meet enterprise and consumer demands for high capacity, high performance, and cost effective data storage. As the number of states in a memory cell increases from multi-level cell (MLC) to triple-level cell (TLC), quad-level cell (QLC), X5 and beyond, it becomes increasingly important for solid state drive (SSD) controllers to manage bit error rates in flash memory to ensure reliable operation of the SSD.